1. Field of the Invention
The present invention relates to a method and apparatus for suspending power, and more particularly, to a method and apparatus for suspending power which increase efficiency and reduce noise.
2. Description of Related Art
Generally, signal processing circuits operating as state machines input data in series, convert the series data to parallel data, and core blocks of the signal processing circuit process the parallel data. A conventional power suspending unit for such a signal processing circuit will now be described.
FIG. 1 is a block diagram illustrating a conventional power suspending unit. As shown in FIG. 1, series input data is received by a converter 14 which converts the series input data into parallel data. A memory 15 stores the parallel data, and outputs the parallel data to a first core block 16 in a series of core blocks 16. Each of the core blocks 16 in the series of core blocks 16 processes the parallel data, and passes the output thereof onto the next core block 16.
As shown in FIG. 1, the power suspending unit further includes a detector 11 which detects a predetermined bit stream in the input data. The predetermined bit stream represents data on which the series of core blocks 16 will not operate.
A counter 12 receives the output of the detector 11, and for each match between the predetermined bit stream and the series input data, increases a count value by 1. When the detector 11 does not determine a match between the predetermined bit stream and the series input data, the counter 12 resets the count value to 0.
A controller 13 receives the count value, and compares the count value to a predetermined threshold. When the controller 13 determines that the count value exceeds the predetermined threshold, the controller 13 outputs a suspending signal to the core blocks 16 to suspend the supply of power to the core blocks 16.
FIG. 2 illustrates the various signals received and produced by the power suspending unit illustrated in FIG. 1. FIG. 2a illustrates the serial input data received by the converter 14 and the detector 11. FIG. 2b illustrates a clock which controls the timing of processing performed in the power suspending unit. FIG. 2c is representative of the predetermined bit stream.
As shown in FIG. 2d, when the predetermined bit stream matches the serial input data, the counter 12 increases the count value by 1. As further shown in FIG. 2d, the count value is increased by 1 until a count value of 10 is reached. For the purposes of explanation, if the predetermined count threshold is established as 9, then when the count value reaches 10 as shown in FIG. 2d, a power suspending signal is output by the controller 13 to the plurality of core blocks 16 to suspend the supply of power to the core blocks 16. As shown in FIG. 2e, the power suspending signal goes from a logic high state to a logic low state to suspend the supply of power to the core blocks 16. Should the count value be reset to 0 upon receipt of series input data which does not match the predetermined bit stream, the suspending signal will resume its high state, and the core blocks 16 will receive power once again.
The above-described conventional power suspending unit suffers from several problems. First, since the power suspension is determined by detecting only the serial input data, the power suspension cannot be controlled on a core block by core block basis. Consequently, core blocks which do not need power are supplied with power; thus, reducing efficiency. In addition, because core blocks which do not need to be operating or supplied with power, the noise level in the system is increased.